Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip binarization step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text and image segmentation step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text line extraction step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text line recognition step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Hardware-software partitioning of the binarization process for the i DocChip system.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: Software

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Hardware-software partitioning of text and image segmentation for the i DocChip system.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: Software

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Hardware-software partitioning of text line extraction for the i DocChip system.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: Software

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip binarization step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text line recognition step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Character-level accuracy of Cloud Vision OCR and i DocChip OCR.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Resource utilization of the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [ 26 , 27 , 28 , 29 ] using Zynq 7045 device @ 166MHz.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Power vs. runtime comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. Runtime is given per image. Single-threaded and multi-threaded implementations are represented as ST and MT . The grid lines show energy consumption in Joules (J).

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Power vs. FPS comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. The grid lines show energy efficiency in FPS/W.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: